The development of semiconductor circuit design and fabrication technologies has resulted in devices such as flash memories, integrated circuits, and logic and other devices of significant complexity and density and which operate at low voltages. Due to the scaling inherent in the design of such complex, dense semiconductor chips, the efficient use of the available silicon area without compromising performance or degrading physical characteristics becomes a significant consideration.
Some chip and wafer designs incorporate a pad area. The pad is typically an area where an interface between the integrated circuit and an external circuit or system can be established. Interfaces between the chip and the external circuits and/or systems can include, for instance, bonding, probing, and packaging. To effectively establish such interfaces, the pad area is typically large, relative to the internal circuit. The pad area thus occupies a significant area of the silicon on the chip.
The pad area is conventionally separated from other circuits in the chip. Separating the pad and the chip internal circuits facilitates probing, bonding, and packaging. The pad separated from them; circuits and devices characteristic of the chip's operation are elsewhere within the chip. FIG. 1 depicts the layout of a conventional semiconductor structure 10. Pad 11 and the active devices of internal circuits 12 of semiconductor device 10 are separated. The internal circuits 12 are located in a non-pad area 13.
Taking one advanced flash memory design as an example, the pad area takes up more area than half of a typical memory sector comprising 512 kilobits. One typical pad size is approximately 80 micrometers by 80 micrometers, thus covering 6,400 square micrometers. Where there are several pads on a chip, such as 40 pads for the exemplary flash memory chip, the amount of silicon area covered by the pad area becomes significant. For instance, the 40 pads on the exemplary flash memory chip, each covering 6,400 square micrometers, together cover over a half million square micrometers of silicon substrate.
Further, electrostatic discharge (ESD) performance is a factor that must be considered in the design of semiconductor structures. Electrical contact with external power sources, physical contact by external objects and other sources can cause potential differences, such as with respect to ground, to be introduced on the pad. The pad is where such contact can be more likely to occur than with respect to internal components of a semiconductor structure.
The pad is connected to internal components however, and introduction of high potentials on the pad can be expressed on components. Modern silicon devices operate at relatively low voltages, such as 1.8 Volts. Some rather common ESD events can introduce potentials on the order of 1,000 Volts or more. Their low operating voltages, constitution, configuration, and/or construction, and their increased circuit densities can render such silicon devices sensitive to the high potentials that can be introduced by ESD.
For instance, the sources and drains of complimentary metal oxide semiconductor (CMOS) transistors can be susceptible to damage. Their gates, which can typically comprise thin oxide films, can be particularly vulnerable. Other components can also be sensitive to the high potentials from ESD and/or to the instantaneous high currents they can introduce. Thus, many silicon structures incorporate ESD protection.
ESD protection can be provided by ESD protective devices, such as transistors. ESD protective devices can become conductive upon gating. ESD protective devices can be controlled by the sensing of a high potential introduction on the pad. Instantaneously sizable currents can flow through the ESD protection devices. This current, which though of short duration (e.g., on the order of 10−9 seconds) can be on the order of an amp or more. This high current can be dissipated in ESD protection resistors connected between the pad and ESD protection transistors, and in series between the sources and drains of ESD protection transistors, as it flows to a typically grounded Vss.
To provide adequate ESD protection, the junctions between the ESD protection resistors and the ESD protection transistors are typically tuned. Such tuning is typically accomplished by varying the resistance of the ESD resistors, such as by techniques employed in the fabrication process of the silicon structure. For handling the currents ESD events can introduce, ESD protection transistors and resistors are typically large, robust devices, relative to the faster transistors and other devices and components. Thus, ESD protection transistors and resistors can occupy a significant area of silicon.
For instance, referring again to FIG. 1, where internal circuits 12 comprise ESD protection transistors and resistors, their size and placement within non-pad area 13 is a typical factor in design and layout considerations for silicon structure 10. Further, their size can provide a constraint on the circuit density achievable for other circuits within silicon structure 10, such as those providing logic, memory, and other functions besides ESD protection.
However, chip size and operating voltages continue to be scaled down, and circuit density scaled up, as technology in the field advances. Thus, the significance of the silicon area covered by the pad area is becoming greater. Further, the impact of the size of ESD protection devices on the silicon area they command is becoming greater as well.
The pad typically has multiple layers of metal, the top layer of which is used for the bonding, probing, and packaging. Lower layers of metal are typically used for introducing pad signals in or out between the internal circuitry of the chip and, for instance, an external system. The bottom level of metal is directly connected to the silicon substrate comprising the chip. However, no active devices are present within the substrate beneath a typical pad.